Integrated circuit chips are conventionally enclosed in a package that provides protection from environmental conditions and enables electrical interconnection between the chip and another electrical component, such as a printed circuit board or a motherboard. A semiconductor package includes a supporting leadframe, a chip electrically coupled to the leadframe, and encapsulating material molded over a surface of the leadframe and the chip. The encapsulating material thus defines an upper exterior surface of the package, while a second non-encapsulated surface of the leadframe defines a lower exterior surface of the package that is configured to be coupled to a printed circuit board.
The leadframe provides a support structure for the package. Quad Flat No Lead (QFN) and Dual Flat No Lead (DFN) are leadless packages where the leadframe is internal to the package and encased by the encapsulating material. When the package is singulated, or severed from its carrier, ends of the leadframe are exposed. Ultimately, a face of the package is attached to a printed circuit board or a motherboard with solder, for example. In some cases, the solder does not bond well to the exposed leadframe ends of the singulated package and fails to form an acceptable fillet of solder along edges of the package. Unacceptable fillets, or imperfect fillets, are associated with unacceptable or imperfect electrical connection between the package (and ultimately the chip) and the printed circuit board or the motherboard.
For these and other reasons there is a need for the present invention.